The present invention relates to a tone generator device which is suitable for connection to a computer system to generate tones using waveform data supplied from the computer system.
The present invention also relates to a tone data processing device and computer system which are suitable for use in tone data generation based on waveform data and pitch information.
In recent years, many personal computers are equipped with a hardware-based tone generator device, which is typically in the form of a tone generator board including a tone generator LSI of predetermined design, to permit various sorts of sound generation processing. According to a typical example of a tone generating principle employed in such a tone generator device, original waveform data are read out from a waveform memory (or a waveform table or wave table) at a rate corresponding to a pitch of each tone to be generated. In this case, the original waveform data stored in the wave table are the results of sampling a tone signal obtained through actual performance of a musical instrument at a predetermined pitch, and a tone data reproduction process is carried out on the basis of tone control data designating a particular pitch, volume, etc. as well as the waveform data stored in the wave table.
Today, tone generator devices connectable to an ISA (Industry Standard Architecture) bus are widely used, as examples of such a hardware-based tone generator device for use with a computer system. The tone generator devices connectable to the ISA bus may be mounted in a variety of ways; for example, they may be mounted on an extension card having a connector attachable into a slot in the ISA bus, or on a system board (mother board) of the computer system. In this type of tone generator device so far proposed, the waveform memory prestoring original waveform data is provided within the tone generator device.
FIG. 16 is a block diagram illustrating a hardware setup of a conventional tone generator device employing the waveform-memory-based tone generating scheme. The illustrated tone generator device is capable of simultaneously generating up to three tones; that is, the maximum number of simultaneously generatable tones in the tone generator device is three. Waveform memory M has prestored therein a plurality of sets of waveform data--in the figure, there are shown only three waveform data sets W1 to W3. Each of the waveform data sets basically comprises waveform sample data for each individual sampling cycle and includes, at its start or head address, data indicative of an original sampling frequency (which will also be called an "input sampling frequency"). The waveform memory M comprises a ROM (Read Only Memory) or RAM (Random Access Memory) and is connected to an internal bus of the tone generator device.
The tone generator device of FIG. 16 further includes an ISA bus interface IF connectable to an ISA bus of a computer system, and address calculating sections A1 to A3 each of which calculates an address to read out a particular sample of the corresponding waveform data W1-W3 from the memory M and then actually reads out the sample of the waveform data W1-W3 from the calculated address. The tone generator device also includes an adder ADD for adding together the waveform sample data output from the address calculating sections A1 to A3, and a D/A converter (DAC) for converting the added result from the adder ADD into an analog signal and then outputting the analog signal to an external device such as a sound system including an amplifier and speaker.
In the tone generator device, a control unit C, in response to an instruction received via the ISA bus IF, supplies the respective head addresses of the waveform data sets (three sets W1 to W3 in the illustrated example) to the corresponding address calculating sections A1 to A3, sets a sampling frequency of the waveform data to be output from each of the address calculating sections A1 to A3 (hereinafter called an "output sampling frequency"), and instructs each of the calculating sections A1 to A3 to start reading out the waveform data.
In response to the readout start instruction given from the control unit C, each of the address calculating sections A1 to A3 reads out the data, indicative of the input sampling frequency, from the head address of the corresponding waveform data set, and then sequentially reads out the waveform sample data, at intervals corresponding to the output sampling frequency, from the succeeding addresses calculated thereby on the basis of the head address and input and output sampling frequencies. If the output sampling frequency is different from the input sampling frequency, most addresses will not actually coincide with predetermined output timing; thus, in such a case, each of the address calculating sections A1 to A3 reads out the waveform sample data from an actually existent address preceding each virtual or imaginary address (containing a decimal portion) that is assumed to be coincident with the predetermined output timing, and generates waveform sample data for that address through interpolation using these data.
The reason why the memory M is provided within the tone generator device and connected to its internal bus instead of a main memory of the computer system being used by the tone generator device is that the data transfer rate of the ISA bus is far lower than the rate normally required for the tone generating processing.
The ISA bus, which has a 16-bit width and operates on an clock pulse frequency (bus clock frequency) of 8.33 MHz, provides a theoretical maximum data transfer rate of 8.33 MB (megabyte)/sec. However, because various items of equipment are usually connected to the ISA bus to share the same bus, they tend to frequently struggle for the bus, which would make an actual data transfer rate of the ISA bus far lower than the above-mentioned theoretical maximum data transfer rate.
Besides, in a situation where the output sampling frequency is different from the input sampling frequency, the address calculating sections A1 to A3, for the interpolation purposes, each read out two waveform sample data at separate timing from two addresses before and after a virtual address coincident with the predetermined output timing, as noted earlier. Because each waveform sample data is generally output in a one-to-one relation to a designated address, outputting two waveform sample data would require an operational sequence of designating a first address, then outputting first waveform sample data from the designated first address, then designating a second address, and then outputting second waveform sample data from the designated second address. Consequently, the quantity of data to be transferred in this case is twice as great as in the case where the output sampling frequency is equal to the input sampling frequency.
For the above-stated reasons, with those conventional tone generator devices expected to simultaneously generating over dozens of tones, it was very difficult to transfer the necessary quantity of the waveform data by way of the ISA bus, and thus there was an absolute need to provide a dedicated waveform memory in the tone generator device. However, because such a waveform memory is an expensive component part, every effort should be made to avoid the provision of the dedicated waveform memory if a reduced cost of the tone generator device is desired.